A typical semiconductor memory device includes a plurality of memory cells or bitcells arranged in arrays, and a memory cell selector means for enabling the selection of a particular memory cell to facilitate the reading of data from, or the writing of data to, that particular memory cell.
For example, a high density dynamic random access memory (DRAM) includes a plurality of core cell blocks, and each core cell block contains several memory cells. The memory cells are metal-oxide semiconductor field-effect transistors (MOSFETs), and each MOSFET acts as a switch. To this end, each pair of MOSFETs is connected to a pair of bit lines (an input/output or I/O port), and the capacitance of each MOSFET can be charged by data. While one of the bit lines is the data itself, the other bit line is the complement data.
A bit line sense amplifier is provided in communication with a pair of bit lines corresponding to a set of memory cells. Each bit line sense amplifier amplifies the data which is read from the corresponding memory cell through the bit line pair or I/O port.
To select a memory cell, a memory column and row address is provided to the DRAM from outside the DRAM. A column decoder decodes this column address which is received from outside the DRAM, and then provides a signal to the corresponding bit line sense amplifier which selects the proper bit line pair therefore selecting the corresponding memory cell which corresponds thereto.
Before a typical read or write cycle, both bit lines of a memory cell are precharged to a relatively high level. Then, during the data read, the memory cell drives the bit lines. As one of the bit lines goes down, the other bit line remains relatively stable. As the one bit line falls, the bit line sense amplifier compares the two bit lines and senses which bit line has a higher charge. The time it takes to determine which bit line has the higher level is the sense time.
It is desirable to provide that the bit line sense amplifier can quickly determine which bit line has the higher level and therefore select the correct bit line or data value. As a result of being able to quickly determine which bit line has the higher charge, data sense time is minimized. When a data read is performed, the bit line which loses charge often falls slowly. This can, for example, be due to high capacitance in the memory array (often caused by a high row count) and the low drive of the memory cell due to its relatively small size. As a result of the falling bit line not falling quickly and the bit line sense amplifier attempting to sense a difference between a stable bit line and a slowly falling bit line, the time in which it takes the bit line sense amplifier to select the correct data value is not minimized. As a result, data sense time is not minimized.